// This is a simple example.
// You can make a your own header file and set its path to settings.
// (Preferences > Package Settings > Verilog Gadget > Settings - User)
//
//		"header": "Packages/Verilog Gadget/template/verilog_header.v"
//
// -----------------------------------------------------------------------------
// Copyright (c) 2014-2024 All rights reserved
// -----------------------------------------------------------------------------
// Author		: HiDark 1173296519@qq.com
// File			: tb_sqrt_u32.sv
// Create		: 2024-01-03 17:18:17
// Description	: 
// Editor		: tab size (4)
// -----------------------------------------------------------------------------
`timescale 1ns/1ps
module tb_sqrt_u32 (); /* this is automatically generated */

	// clock
	logic clk;
	initial begin
		clk = '0;
		forever #(0.5) clk = ~clk;
	end

	// asynchronous reset
	logic rst_n;
	initial begin
		rst_n <= 'd0;
		#5
		rst_n <= 'd1;
	end

	// (*NOTE*) replace reset, clock, others
	logic        vld_in;
	logic [31:0] x;
	logic        vld_out;
	logic [16:0] y;

	sqrt_u32 #(.DW(32)) inst_sqrt_u32  (.clk(clk), .rst_n(rst_n), .vld_in(vld_in), .x(x), .vld_out(vld_out), .y(y));

	task init();
		vld_in <= 'd0;
		x      <= 'd0;
	endtask

	initial begin
		// do something
		init();
		repeat(10)@(posedge clk);
		repeat(1)@(posedge clk);
		vld_in <= 'd1;
		x      <= 'd4294967295;
		repeat(1)@(posedge clk);
		vld_in <= 'd0;	
		repeat(17)@(posedge clk);			
	    vld_in <= 'd1;
		x      <= 'd256;
	   repeat(1)@(posedge clk);
		vld_in <= 'd0;	
		repeat(17)@(posedge clk);			
	    vld_in <= 'd1;
		x      <= 'd2147483648;		
	   repeat(1)@(posedge clk);
		vld_in <= 'd0;	
		repeat(17)@(posedge clk);			
	    vld_in <= 'd1;
		x      <= 'd255;		
		repeat(20)@(posedge clk);
		$finish;
	end
endmodule
